As digital processors advance in complexity, the use of limited internal memory is becoming increasingly popular as opposed to always having to communicate with memory external to the processor. In digital filtering, a need often exists to read an operand from memory, perform an operation on the operand and then write the modified operand back to memory. Such an operation is very common in adaptive filters. With pipelined processor architectures, it is possible to execute many operations during a single processor machine cycle, where a cycle is typically defined as the time between successive inputting of data to an arithmetic unit (AU). Therefore, in order to read a first operand from memory, modify a second operand in an AU, and write a third operand back to the memory in a pipelined architecture, at least two processor cycles are required. Two cycles are required in order to avoid a data collision in reading and writing data to the memory at the same time. Such systems which accomplish read, modify and write operations in a memory typically utilize virtual dual-port RAMs requiring processor wait states and port arbitration.